Mirror of FPGC5

bart 997e6c76d0 Backported benchmarking program from FPGC6 for comparisons. 1 year ago
Assembler c6e849bf14 Added ASM optimizer option in the Python version which recursively removes all uncalled functions and global variables. Updated compile scripts to use this option and made some fixes to BDOS to prevent removal of uncalled ASM define workaround functions 2 years ago
BCC 997e6c76d0 Backported benchmarking program from FPGC6 for comparisons. 1 year ago
Documentation afa9e59f74 ASM works now. Restructured some file and modified some files and filenames so they can be copied directly 2 years ago
Graphics ddb7182dec Added motion configuration file for HDMI capture streaming 2 years ago
MidiConverter d0acf22bfa Removed old files from project 2 years ago
PCB 80ae82bbab Minor project cleanup and changes 2 years ago
Programmer b46c9e8d80 Added retries to netUpload/Flash.py. Created script that sends all userBDOS files to FPGC. Made seperate script to send single commands to BDOS. Had to add an echo in HIDloader for commands to know when they are parsed so the host can close the socket. 2 years ago
Quartus 8832d89b38 ALU MULT is now always signed. More work on BCC on FPGC 2 years ago
SublimeText3 80ae82bbab Minor project cleanup and changes 2 years ago
Verilog 8832d89b38 ALU MULT is now always signed. More work on BCC on FPGC 2 years ago
.gitignore a86f6febf8 updated gitignore with new BCC path 2 years ago
LICENSE.txt 3594ec88f0 Init from FPGC4 2 years ago
README.md b855cfbc37 Update readme after starting FPGC6, fixing documentation link 1 year ago

README.md

FPGC5

My big project, basically started in July 2019 as FPGC3 (versions 1 and 2 do not count). Project exists to learn more about the fundamentals of computers and to improve my Verilog skills, while also designing my own "environment" (PCB, Compilers, OS, etc.) around it.

FPGC is a completely self designed computer, implemented in an EP4CE15 FPGA.

FPGC Logo

Project Wiki (not fully up to date, but contains a lot of info)